neorv32-riscof
neoTRNG
| neorv32-riscof | neoTRNG | |
|---|---|---|
| 2 | 10 | |
| 24 | 156 | |
| - | - | |
| 9.1 | 7.3 | |
| 7 days ago | about 2 months ago | |
| Python | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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neorv32-riscof
neoTRNG
- A really tiny and platform-independent true random number generator for FPGAs and ASICs
- Show HN: A tiny and platform-agnostic true random number generator for FPGA/ASIC
-
Synthesizable LFSR counter (feedback 16,13)
This TRNG (VHDL) provides some kind of "imulation mode where the entropy source is replaced by a LFSR. When simulated, the testbench prints the random data to the simulator console. Maybe this can help as starting point.
- A tiny and platform-agnostic TRUE random number generator for any FPGA
- A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- Show HN: A Tiny and Platform-Agnostic True Random Number Generator for Any FPGA
- A Tiny and Platform-Independent True Random Number Generator for any FPGA.
What are some alternatives?
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpu - IEEE 754 floating point library in system-verilog and vhdl
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
potato - A simple RISC-V processor for use in FPGA designs.