ndk-app-minimal
neo430
| ndk-app-minimal | neo430 | |
|---|---|---|
| 4 | 3 | |
| 23 | 178 | |
| - | - | |
| 8.2 | 2.8 | |
| 17 days ago | over 2 years ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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ndk-app-minimal
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A simple high-throughput open-source packet generator
as the title says, I'm looking to build a simple packet generator (a PCAP (re)player might be a better term), mainly for load-testing network devices. The goal is to be able to fully congest a 400G Ethernet line. To achieve such a high throughput rate, I plan to use the NDK platform to build my application.
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Xilinx alternatives??
We have few Intel Agilex I-Series FPGA boards in our lab. It can do 400G Ethernet 8x56Gb or 4x112Gb (F-Tile), PCIe Gen5 x16 (R-Tile) and CXL IP is for a fee, I think. You can find an example of using F/R-Tile in our open-source NDK: https://github.com/CESNET/ndk-app-minimal
- The Network Development Kit for FPGA cards in version 0.3.1 released
- The Network Development Kit for FPGA cards released as open-source
neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
What are some alternatives?
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
serv - SERV - The SErial RISC-V CPU
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
SoC - Github Repo for Embedded FPGA course by Vincent Claes
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
simple-riscv - A simple three-stage RISC-V CPU
Arcade_Galaga - Galaga Arcade Core
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
betrusted-wiki - Looking for docs on Precursor/Betrusted? Start here.