naja VS naja-verilog

Compare naja vs naja-verilog and see what are their differences.

naja

Structural Netlist API (and more) for EDA post synthesis flow development (by najaeda)
netlist eda semiconductor Verilog Asic Fpga CPP
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naja-verilog

A standalone structural (gate-level) verilog parser (by najaeda)
CPP eda netlist netlist-parser semiconductor Verilog electronic-design-automation Parser
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naja naja-verilog
4 2
43 21
- -
9.0 7.6
7 days ago about 1 month ago
Python C++
Apache License 2.0 Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

naja

Posts with mentions or reviews of naja. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-10-11.

naja-verilog

Posts with mentions or reviews of naja-verilog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-10-11.
  • Naja-Verilog: stand-alone structural (gate-level) parser
    2 projects | /r/FPGA | 11 Oct 2023
    Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
  • Show HN: Naja-Verilog – Structural Verilog Parser
    2 projects | news.ycombinator.com | 24 Mar 2023

What are some alternatives?

When comparing naja and naja-verilog you can also consider the following projects:

metron - A C++ to Verilog translation tool with some basic guarantees that your code will work.

Degate - A modern and open-source cross-platform software for chips reverse engineering.

verilator - Verilator open-source SystemVerilog simulator and lint system

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

rggen - Code generation tool for control and status registers

Beagle_SDR_GPS - KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

neorv32-verilog - ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.

fpga_floorplanning - NTHU CS5160 FPGA結構及設計自動化 麥偉基 Final Project

naja vs metron naja-verilog vs Degate naja vs verilator naja-verilog vs hdlConvertor naja vs rggen naja-verilog vs verilator naja vs Beagle_SDR_GPS naja-verilog vs Surelog naja vs neorv32-verilog naja-verilog vs spydrnet naja vs fpga_floorplanning