minimax
black-parrot
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minimax | black-parrot | |
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13 | 5 | |
194 | 525 | |
- | 3.6% | |
2.9 | 8.2 | |
8 days ago | 24 days ago | |
Verilog | SystemVerilog | |
BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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minimax
- Is the 6502 a RISC or CISC processor? (2005)
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A Single-Cycle 64-Bit RISC-V Register File
On FPGAs, a register file probably fits better into distributed RAM than block RAM.
On Xilinx, for example: a 64-bit register file doesn't map efficiently to Xilinx's RAMB36 primitives. You'd need 2 RAMB36 primitives to provide a 64-bit wide memory with 1 write port and 2 read ports, each addressed separately. Only 6% (32 of 512) entries in each RAMB36 are ever addressable. It's this inefficient because ports, not memory cells, are the contented resource and BRAMs geometries aren't that elastic.
A 64-bit register file in distributed RAM, conversely, is a something like an array of DPRAM32 primitives (see, for example, UG474). Each register would still be stored multiple times to provide additional ports, but depending on the fabric, there's less (or no) unaddressed storage cells.
The Minimax RISC-V CPU (https://github.com/gsmecher/minimax; advertisement warning: my project) is what you get if you chase efficient mapping of FPGA memory primitives (both register-file and RAM) to a logical conclusion. Whether this is actually worth hyper-optimizing really depends on the application. Usually, it's not.
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Verilator - Do I need to maintain two testbench suits?
I haven't used it on a huge design (I'm usually a VHDL person), but it was a hassle-free replacement for iverilog when regression testing Minimax. Performance is substantially better; compilation times are worse.
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Zylin ZPU: The worlds smallest 32 bit CPU with GCC toolchain
Note that you can't compare LUT4 results (ZPU @ 440 LUTs) against LUT6 results (PicoRV32 @ 750 LUTs). The ZPU is remarkably small, and it's a bigger gap than a direct comparison shows.
SERV is a fair comparison, since it's architected for 4LUTs and I suspect the synthesis results come from iCE40 tools.
I have a contender in the "very small" space, too [1], although I don't claim it's as mature or complete as SERV. (If Minimax was excluded from your post on the basis of insanity, I'm OK with that.)
[1] https://github.com/gsmecher/minimax
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Senior Design Project Ideas?
I develop Minimax (https://github.com/gsmecher/minimax), an open-source RISC-V implementation. It's currently written in both VHDL and Verilog (the two implementations are equivalent, though I am likely to drop the VHDL implementation if it's too much work to keep them both.)
- Compiled and Interpreted Languages: Two Ways of Saying Tomato
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PicoBlaze in Verilog / Vivado
The best point-of-entry for "tiny" MCUs these days is FemtoRV32-Quark or SERV. I also maintain my own small RISC-V core (Minimax), though it's early on in graduating from "experiment" to "real design".
- Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU
- Minimax: A Compressed-First, Microcoded RISC-V CPU
black-parrot
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Verilator - Do I need to maintain two testbench suits?
Another option is to have a single verilog testbench with clock and reset ports driven by verilator:https://github.com/black-parrot/black-parrot/blob/master/bp_top/test/tb/bp_tethered/test_bp.cpphttps://github.com/black-parrot/black-parrot/blob/master/bp_top/test/tb/bp_tethered/testbench.sv
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Which FPGA for getting into RISC-V?
It depends drastically on the core and configuration, but a default configured BlackParrot: https://github.com/black-parrot/black-parrot takes up about 50% of Z2 resources without any FPGA-specific tweaks.
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ASIC roundup of open source RISC-V CPU cores
Whoops, read the blog “no sram”. Would love to get my project https://github.com/black-parrot/black-parrot/tree/master on there. Do you have a sense for how many instances your flow could support? We use hardened srams for our caches which are minimally 8kB each at the moment.
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Contribution to Open Source Hardware Projects
What's your background? We have starting projects in a few areas on our RV64 multicore project: https://github.com/black-parrot/black-parrot
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A case for J standard extension?
https://github.com/black-parrot/black-parrot has coherent I$/D$
What are some alternatives?
ZPUFlex - A highly-configurable and compact variant of the ZPU processor core
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Artix-7-HDMI-processing - Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
sulong - Obsolete repository. Moved to oracle/graal.
serv - SERV - The SErial RISC-V CPU
riscof
ch32v003 - CH32V003 is an ultra-cheap RISC-V MCU with 2KB SRAM, 16KB flash, and up to 18 GPIOs that sells for under $0.10
mini-rv32ima - A tiny C header-only risc-v emulator.
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
pinwheel - A tiny RISC-V processor for hard-real-time FPGA-based applications.