minimax
mini-rv32ima
Our great sponsors
minimax | mini-rv32ima | |
---|---|---|
13 | 16 | |
194 | 1,479 | |
- | - | |
2.9 | 6.6 | |
8 days ago | 14 days ago | |
Verilog | C | |
BSD 3-clause "New" or "Revised" License | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
minimax
- Is the 6502 a RISC or CISC processor? (2005)
-
A Single-Cycle 64-Bit RISC-V Register File
On FPGAs, a register file probably fits better into distributed RAM than block RAM.
On Xilinx, for example: a 64-bit register file doesn't map efficiently to Xilinx's RAMB36 primitives. You'd need 2 RAMB36 primitives to provide a 64-bit wide memory with 1 write port and 2 read ports, each addressed separately. Only 6% (32 of 512) entries in each RAMB36 are ever addressable. It's this inefficient because ports, not memory cells, are the contented resource and BRAMs geometries aren't that elastic.
A 64-bit register file in distributed RAM, conversely, is a something like an array of DPRAM32 primitives (see, for example, UG474). Each register would still be stored multiple times to provide additional ports, but depending on the fabric, there's less (or no) unaddressed storage cells.
The Minimax RISC-V CPU (https://github.com/gsmecher/minimax; advertisement warning: my project) is what you get if you chase efficient mapping of FPGA memory primitives (both register-file and RAM) to a logical conclusion. Whether this is actually worth hyper-optimizing really depends on the application. Usually, it's not.
-
Verilator - Do I need to maintain two testbench suits?
I haven't used it on a huge design (I'm usually a VHDL person), but it was a hassle-free replacement for iverilog when regression testing Minimax. Performance is substantially better; compilation times are worse.
-
Zylin ZPU: The worlds smallest 32 bit CPU with GCC toolchain
Note that you can't compare LUT4 results (ZPU @ 440 LUTs) against LUT6 results (PicoRV32 @ 750 LUTs). The ZPU is remarkably small, and it's a bigger gap than a direct comparison shows.
SERV is a fair comparison, since it's architected for 4LUTs and I suspect the synthesis results come from iCE40 tools.
I have a contender in the "very small" space, too [1], although I don't claim it's as mature or complete as SERV. (If Minimax was excluded from your post on the basis of insanity, I'm OK with that.)
[1] https://github.com/gsmecher/minimax
-
Senior Design Project Ideas?
I develop Minimax (https://github.com/gsmecher/minimax), an open-source RISC-V implementation. It's currently written in both VHDL and Verilog (the two implementations are equivalent, though I am likely to drop the VHDL implementation if it's too much work to keep them both.)
- Compiled and Interpreted Languages: Two Ways of Saying Tomato
-
PicoBlaze in Verilog / Vivado
The best point-of-entry for "tiny" MCUs these days is FemtoRV32-Quark or SERV. I also maintain my own small RISC-V core (Minimax), though it's early on in graduating from "experiment" to "real design".
- Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU
- Minimax: A Compressed-First, Microcoded RISC-V CPU
mini-rv32ima
-
Driver hack lets you run Linux after Windows BSODs, no reboot required
It does emulate RiscV that runs Linux, so why not call it a Linux emulator?
Though https://github.com/cnlohr/mini-rv32ima is indeed impressively small. Here's the dispatch switch-case: https://github.com/cnlohr/mini-rv32ima/blob/eeeaaa0609558c84...
-
I boot Linux 6.1 on atmega328p
Yes you read it correctly. This is not April Joke. This is real Linux 6.1 running on real atmega328p clocked at 16MHz. Basically it's an optimized version of mini-rv32ima running on Arduino UNO with SD card swap. The entire code is written in C99.
-
Writing a Really Tiny RISC-V Emulator: rv32ima/Zifencei+Zicsr... sort of
repo:
-
Fun, or pure magic: RISC-V rv32ima emulator running busybox linux
git clone https://github.com/cnlohr/mini-rv32ima.git cd mini-rv32ima/ git reset --hard f5154edc2894c2624361ef26ad8c3e6ebd23dea3 # workaround for now make testdlimage
-
Zylin ZPU: The worlds smallest 32 bit CPU with GCC toolchain
Not GP, but this might scratch your itch https://github.com/cnlohr/mini-rv32ima
-
RVVM – The RISC-V Virtual Machine
So is this, even more so in my taste:
https://github.com/cnlohr/mini-rv32ima/blob/master/mini-rv32...
A RISC-V emulator in one include file.
- Making an emulator: Questions
- Open-source RISC-V simulator suggestions?
-
Embedded Systems Weekly #129
Writing a Really Tiny RISC-V Emulator It's maybe the tiniest RISC-V emulator around. It is all in one unique function of ~400 lines, but it can run Linux and various executables on it. The tiny C header-only risc-v emulator code is on Github with everything needed to make it run yourself. It's a really impressive work which deserves to be highlighted,
-
I got Linux running INSIDE of Team Fortress 2!
riscv-vscript is a port of mini-rv32ima to VScript (Squirrel3) that:
What are some alternatives?
ZPUFlex - A highly-configurable and compact variant of the ZPU processor core
8086tiny - 8086tiny interpreter by Adrian Cable, taken from http://www.megalith.co.uk/8086tiny/
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
Ripes - A graphical processor simulator and assembly editor for the RISC-V ISA
Artix-7-HDMI-processing - Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
whisper
sulong - Obsolete repository. Moved to oracle/graal.
pinwheel - A tiny RISC-V processor for hard-real-time FPGA-based applications.
serv - SERV - The SErial RISC-V CPU
EightThirtyTwo - An experimental CPU core with 8-bit instruction words and 32-bit registers
riscof
riscv-vm - A Small RISC-V Virtual Machine