m6502
nmigen
| m6502 | nmigen | |
|---|---|---|
| 2 | 3 | |
| 3 | 643 | |
| - | 1.2% | |
| 3.8 | 1.8 | |
| almost 3 years ago | over 2 years ago | |
| Python | Python | |
| GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
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m6502
nmigen
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Help a newbie
You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
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Do these work as JTAG programmers?
Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
amaranth - A modern hardware definition language and toolchain based on Python
myhdl - The MyHDL development repository
py65 - Emulate 6502-based microcomputer systems in Python
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
pyverilator - Python wrapper for verilator model
n6800 - A 6800 CPU written in nMigen
openFPGALoader - Universal utility for programming FPGA
awesome-latticeFPGAs - :book: List of FPGA Lattice boards using open tools
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.