fpga_screensaver VS Cores-VeeR-EL2

Compare fpga_screensaver vs Cores-VeeR-EL2 and see what are their differences.

fpga_screensaver

This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board. (by sifferman)
Fpga Fusesoc
Source Code
ieee.sifferman.dev
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Cores-VeeR-EL2

VeeR EL2 Core (by chipsalliance)
el2 Verilator western-digital Riscv risc-v Processor open-source-hardware Fusesoc Rtl Fpga Axi4 ahb-lite Riscv32 asic-design
Source Code
chipsalliance.github.io
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fpga_screensaver Cores-VeeR-EL2
1 1
6 223
- 1.3%
3.3 9.0
9 months ago 7 days ago
SystemVerilog SystemVerilog
The Unlicense Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

fpga_screensaver

Posts with mentions or reviews of fpga_screensaver. We have used some of these posts to build our list of alternatives and similar projects.
  • Best fpga for begginers
    1 project | /r/FPGA | 9 Jun 2023
    This is a simple VGA project I did for the Tang Nano: https://github.com/sifferman/fpga_screensaver

Cores-VeeR-EL2

Posts with mentions or reviews of Cores-VeeR-EL2. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-09-08.

What are some alternatives?

When comparing fpga_screensaver and Cores-VeeR-EL2 you can also consider the following projects:

openfpga-NES - NES for the Analogue Pocket

riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine

Cores-VeeR-EH1 - VeeR EH1 core

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

rocket-chip - Rocket Chip Generator

VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

WDMC-Ex2-Ultra - Enhanced Ram Disk and Linux Kernel for WD My Cloud Ex2 Ultra

fpga_screensaver vs openfpga-NES Cores-VeeR-EL2 vs riscv-boom fpga_screensaver vs Cores-VeeR-EH1 Cores-VeeR-EL2 vs Cores-VeeR-EH1 fpga_screensaver vs cva6 Cores-VeeR-EL2 vs projf-explore fpga_screensaver vs projf-explore Cores-VeeR-EL2 vs cv32e40p Cores-VeeR-EL2 vs rocket-chip Cores-VeeR-EL2 vs VeriGPU Cores-VeeR-EL2 vs scr1 Cores-VeeR-EL2 vs WDMC-Ex2-Ultra