cariboulite
spu32
cariboulite | spu32 | |
---|---|---|
4 | 1 | |
1,049 | 61 | |
1.4% | - | |
8.8 | 0.0 | |
about 2 months ago | about 2 years ago | |
C | C | |
- | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cariboulite
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Real hidden gems when it comes to self hosting
Finally, you can find great projects by browsing Github topics for sqlite, flat-file database, or the self-hosted tag. Thanks for reading my thesis. Also, why don't you go build a mechanical keyboard, a soldering iron, turn your Raspberry Pi into a Tx/Rx 6GHz SDR, or get a CS degree?
- What’s the best alternative to RTL that’s not TOO expensive but does TX/RX? There seems to be a lot of choices.
- Cariboulabs/cariboulite – turn any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
spu32
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Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
What are some alternatives?
mayhem-firmware - Custom firmware for the HackRF+PortaPack H1/H2
shecc - A self-hosting and educational C optimizing compiler
hackrf - low cost software radio platform
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
portapack-havoc - Custom firmware for the HackRF SDR + PortaPack H1 addon
quasiSoC - Linux capable RISC-V SoC designed to be readable and useful.
nexmon - The C-based Firmware Patching Framework for Broadcom/Cypress WiFi Chips that enables Monitor Mode, Frame Injection and much more
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
pikrellcam - Raspberry Pi motion vector detection program with OSD web interface.
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
csdr - A simple DSP library and command-line tool for Software Defined Radio.
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!