VHDL-Issues
SpinalHDL
VHDL-Issues | SpinalHDL | |
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11 | 8 | |
- | 1,531 | |
- | 2.0% | |
- | 9.8 | |
- | about 15 hours ago | |
Scala | ||
- | GNU General Public License v3.0 or later |
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VHDL-Issues
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What would be your go-to solution for configurable number of entity's output signals? (VHDL)
Not possible until VHDL 2019 using conditional analysis (basically VHDL pre-processor). This is supported by the newest intel Pro tools and most paid for simulators. A better version, without having to use conditional analysis, is proposed for VHDL 202X : https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/205
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How to create a register array in VHDL in which each entry in the array has input and outputting on the same cycle, behaves as a register, and is coded as an entry in an array?
You are confusing all sorts of VHDL terms. my_array is simply an array object, it has no ports. Ports exist on an entity. Vhdl has no direct knowledge of underlying hardware, hence register_array would not be suitable as a VHDL keyword. If you think it is, you need to suggest it at https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why are there only 3 languages for FPGA development?
For those who would like to see additional features / simplifications in VHDL, the working group accepts issues at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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A new suggested keyword register_array for VHDL
Reddit is not really a great place to suggest language modifications. The vhdl committee have a gitlab issues page where new language ideas can be submitted.. https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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sphinx-vhdl: Automatic generation of documentation from VHDL
See: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- Include I/O ports using parameter
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Active Busy VHDL Discussion Groups?
You too can contribute to the next revision of VHDL at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Why is verilog more popular?
The IEEE WG welcomes new participants - especially people like yourself who have some experience. Got a good idea, you can interact with the VHDL WG community here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
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Signed Type vs Integer Type
If you want to get involved with language updates, we now use git issues. See here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues
- VHDL Standards and You ...
SpinalHDL
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1800-2023 – IEEE Standard for SystemVerilog
I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.
I really like what Zig and C++ are doing with `const`.
https://ikrima.dev/dev-notes/zig/zig-metaprogramming/
Have you looked at Spinal?
https://github.com/SpinalHDL/SpinalHDL
https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Simple skid buffer implementation
I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.
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Why are there only 3 languages for FPGA development?
Don’t forget SpinalHDL that was forked off of Chisel 2 I believe. These DSLs really leveraged the software features of Scala to help build generalised/modular systems. And are generally a quality of life improvement in the language features available.
- SpinalHDL – A high level hardware description language based on Scala
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
- Chisel/Firrtl Hardware Compiler Framework
What are some alternatives?
sphinx-vhdl
chisel - Chisel: A Modern Hardware Design Language
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
amaranth - A modern hardware definition language and toolchain based on Python
litex - Build your hardware, easily!
chiselverify - A dynamic verification library for Chisel.
litepcie - Small footprint and configurable PCIe core
circt - Circuit IR Compilers and Tools
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
verilog-ethernet - Verilog Ethernet components for FPGA implementation
chiseltest - The batteries-included testing and formal verification library for Chisel-based RTL designs.
myhdl - The MyHDL development repository