What would be your go-to solution for configurable number of entity's output signals? (VHDL)

• VHDL-Issues

  11 - -

Not possible until VHDL 2019 using conditional analysis (basically VHDL pre-processor). This is supported by the newest intel Pro tools and most paid for simulators. A better version, without having to use conditional analysis, is proposed for VHDL 202X : https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/205

• RedPitaya-FPGA

  1 28 8.1 Tcl

  Repository for FPGA projects

  

You could use this implementation as a reference: https://github.com/RedPitaya/RedPitaya-FPGA/blob/master/rtl/asg.sv It is similar to what you are trying to make.

• InfluxDB

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