Main_MiSTer VS litex

And for a fancier alternative, consider miSTer.

You need to update your mister ini. The ypbpr=1 setting is no longer supported and you need to use vga=ypbpr instead. This was changed when s video got added. You can get the latest ini here https://github.com/MiSTer-devel/Main_MiSTer/blob/master/MiSTer.ini

I went ahead and read the thread on it and... yeah, Sorg is firm. He cites a couple reasons which I understand though fundamentally disagree with. Oh well.

Consider getting an actual A500 or a miSTer at that point.

MisterFPGA project on GitHub

Just get a pc and get a new microsd card and follow this https://github.com/MiSTer-devel/Main_MiSTer/wiki/Setup-Guide and see if it works.

Hello all, I recently started Youtube channel, I want to focus on gaming & especially retro games/systems. Each week I plan to upload video of this type, I have interest in both hardware emulation eg Mister fpga & software emulation such as; OpenEmu etc. For example FPGA emulation acts the same as original hardware so it is higher quality & software emulation relies solely on mimicking original hardware. Which do you prefer/why? https://github.com/MiSTer-devel/Main_MiSTer/wiki/Arcade-Cores-List The link above; will be were I go through each core & decide which to make Youtube content of.

https://github.com/enjoy-digital/litex

they have tutorials, you can get compatible boards for around $20

With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.

To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen

If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.

I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.