ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32 (by FelipeFFerreira)
airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors. (by Fraunhofer-IMS)
ITA-CORES | airisc_core_complex | |
---|---|---|
1 | 1 | |
34 | 73 | |
- | - | |
8.7 | 4.8 | |
6 months ago | 6 months ago | |
Verilog | Verilog | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ITA-CORES
Posts with mentions or reviews of ITA-CORES.
We have used some of these posts to build our list of alternatives
and similar projects.
airisc_core_complex
Posts with mentions or reviews of airisc_core_complex.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-10.
What are some alternatives?
When comparing ITA-CORES and airisc_core_complex you can also consider the following projects:
riscv - RISC-V CPU Core (RV32IM)
Hazard3 - 3-stage RV32IMACZb* processor with debug
friscv - RISCV CPU implementation in SystemVerilog
biriscv - 32-bit Superscalar RISC-V CPU
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
serv - SERV - The SErial RISC-V CPU
riscv-isa-manual - RISC-V Instruction Set Manual