ITA-CORES VS RISC-V

Compare ITA-CORES vs RISC-V and see what are their differences.

ITA-CORES

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32 (by FelipeFFerreira)
Chip Framework physical-design physical-design-automation risc-v Rv32i Asic femtorv32
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RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension (by AngeloJacobo)
risc-v Verilog Rv32i rv32 Cpu Riscv 5-stage-pipeline Formal Verification
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ITA-CORES RISC-V
1 1
34 45
- -
8.7 7.6
6 months ago 5 months ago
Verilog Verilog
GNU General Public License v3.0 or later MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

ITA-CORES

Posts with mentions or reviews of ITA-CORES. We have used some of these posts to build our list of alternatives and similar projects.

RISC-V

Posts with mentions or reviews of RISC-V. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing ITA-CORES and RISC-V you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

fpga_riscv_cpu - fpga verilog risc-v rv32i cpu

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

riscv - RISC-V CPU Core (RV32IM)

RISC-V vs biriscv RISC-V vs fpga_riscv_cpu RISC-V vs neorv32 RISC-V vs darkriscv RISC-V vs riscv