Compliance-Tests
neo430
| Compliance-Tests | neo430 | |
|---|---|---|
| 1 | 3 | |
| 25 | 178 | |
| - | - | |
| 4.0 | 2.8 | |
| 6 days ago | over 2 years ago | |
| VHDL | VHDL | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Compliance-Tests
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VHDL Testbench Library Comparison
There is an initiative for feature support here: https://github.com/VHDL/Compliance-Tests/ but is has not been active for over a year. With a compliance test anyone can test their own simulator or simulators they are evaluating. A public comparison is trickier as such benchmarking is typically prohibited by the license.
neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
serv - SERV - The SErial RISC-V CPU
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
SoC - Github Repo for Embedded FPGA course by Vincent Claes
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
simple-riscv - A simple three-stage RISC-V CPU
Arcade_Galaga - Galaga Arcade Core
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
betrusted-wiki - Looking for docs on Precursor/Betrusted? Start here.