BYU_PYNQ_PR_Video_Pipeline
The Demo that was presented at FCCM. (by byuccl)
litex
Build your hardware, easily! (by enjoy-digital)
| BYU_PYNQ_PR_Video_Pipeline | litex | |
|---|---|---|
| 2 | 29 | |
| 14 | 2,688 | |
| - | - | |
| 0.0 | 9.7 | |
| over 5 years ago | 6 days ago | |
| Jupyter Notebook | C | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
BYU_PYNQ_PR_Video_Pipeline
Posts with mentions or reviews of BYU_PYNQ_PR_Video_Pipeline.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-15.
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References for video system design on FPGAs.
Here is my example: Thesis: https://scholarsarchive.byu.edu/etd/8620/ HW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline_Hardware SW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
litex
Posts with mentions or reviews of litex.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-11-06.
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FPGA Dev Boards for $150 or Less
https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
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Sunset TCL scripts ?
LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.
- synthesizing and using the Ibex RISC-V core
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Been messing around with litex and migen on my Tang Primer 20K
To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen
- CPU design for college project
- How can I learn about RISC-V and use case? I want to do a project for begginers
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
- LiteX: Build Hardware Easily
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Using FPGAs for computations as a beginner
I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.
What are some alternatives?
When comparing BYU_PYNQ_PR_Video_Pipeline and litex you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
nmigen-tutorial - A tutorial for using nmigen
SpinalHDL - Scala based HDL
corundum - Open source FPGA-based NIC and platform for in-network compute
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
verilog-wishbone - Verilog wishbone components
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
BYU_PYNQ_PR_Video_Pipeline vs verilog-ethernet
litex vs nmigen-tutorial
BYU_PYNQ_PR_Video_Pipeline vs SpinalHDL
litex vs SpinalHDL
BYU_PYNQ_PR_Video_Pipeline vs corundum
litex vs fusesoc
BYU_PYNQ_PR_Video_Pipeline vs verilog-wishbone
litex vs SaxonSoc
BYU_PYNQ_PR_Video_Pipeline vs satcat5
litex vs openwifi
BYU_PYNQ_PR_Video_Pipeline vs FPGA_RealTime_and_Static_Sobel_Edge_Detection
litex vs verilog-ethernet