yosys

Open-source projects categorized as yosys
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Language: + Python + Makefile + C + JavaScript + Haskell + SystemVerilog + VHDL + Dockerfile + Rust + HTML
Topics: Fpga Verilog Hdl nmigen vivado
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Top 17 yosy Open-Source Projects

  • amaranth

    A modern hardware definition language and toolchain based on Python

  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

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  • cariboulite

    CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

  • nmigen

    A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

  • edalize

    An abstraction library for interfacing EDA tools

  • netlistsvg

    draws an SVG schematic from a JSON netlist

  • sv2v

    SystemVerilog to Verilog conversion

    • Project mention: Verilog functions and wires | /r/Verilog | 2023-06-11

    I see what you mean by some online examples adding begin...end in functions. They are not actually required, and many people choose to leave it out (sv2v, lowRISC, BSG). I don't believe there is a benefit to adding them, and it just creates more opportunities for bugs that compilers/linters cannot check.

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  • eurorack-pmod

    Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.

  • neorv32-setups

    📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

    • Project mention: How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG? | /r/FPGA | 2023-08-03

    Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.

  • sphinxcontrib-hdl-diagrams

    Sphinx Extension which generates various types of diagrams from Verilog code.

  • eda_tools

    A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.

  • fusesoc_template

    Example of how to get started with olofk/fusesoc.

  • icicle

    An OSS CAD Suite Version Manager (by nishtahir)

  • m6502

    6502 CPU implementation written in nMigen

  • FPGA-blinky

    • Project mention: collection of templates (with Makefile) for different FPGA's and toolchains | /r/FPGA | 2023-11-08

  • tang-doc

    Documentation for Lichee Tang

  • verilog_template

    A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

  • SaaSHub

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

yosys related posts

  • Verilog functions and wires

    1 project | /r/Verilog | 11 Jun 2023

  • [D][P] Represent Analog Circuits as Graphs

    3 projects | /r/MachineLearning | 15 Apr 2023

  • Generation of "high level" block diagram based on verilog files

    1 project | /r/FPGA | 28 Feb 2023

  • Logic Primitive Transformations with Yosys Techmap

    1 project | news.ycombinator.com | 28 Nov 2022

  • HDL desugaring

    1 project | /r/FPGA | 12 Aug 2022

  • Compilation of open source tools in Docker

    1 project | /r/FPGA | 4 Jun 2022

  • FPGA Interchange format to enable interoperable FPGA tooling

    6 projects | news.ycombinator.com | 12 Feb 2022
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    www.influxdata.com | 6 May 2024
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Index

What are some of the best open-source yosy projects? This list will help you:

Project Stars
1 amaranth 1,444
2 openlane 1,191
3 cariboulite 1,035
4 nmigen 643
5 edalize 593
6 netlistsvg 585
7 sv2v 475
8 eurorack-pmod 159
9 neorv32-setups 53
10 sphinxcontrib-hdl-diagrams 50
11 eda_tools 34
12 fusesoc_template 12
13 icicle 5
14 m6502 3
15 FPGA-blinky 3
16 tang-doc 3
17 verilog_template 0

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