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netlistsvg reviews and mentions
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Generation of "high level" block diagram based on verilog files
Maybe this: https://github.com/nturley/netlistsvg
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Logic Primitive Transformations with Yosys Techmap
Great article. Especially needed since Yosys is very difficult to use.
One tip, maybe. Yosys's Graphviz output is frankly incomprehensible shit, and Graphviz isn't very good at laying out these sorts of graphs. But it also can output the information to JSON with the write_json command which lets you use other better tools, e.g. https://github.com/nturley/netlistsvg
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FPGA Interchange format to enable interoperable FPGA tooling
Soon: there are 15 different formats for passing netlists around.
I have very little hope that any netlist format that comes from Yosys. Not only has it changed a couple times in the last years, but the latest iteration is some JSON-based monstrosity that has to be by far the most inconvenient netlist format ever created (see https://github.com/nturley/netlistsvg/blob/master/test/digit... ) .
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A note from our sponsor - InfluxDB
www.influxdata.com | 10 May 2024
Stats
nturley/netlistsvg is an open source project licensed under MIT License which is an OSI approved license.
The primary programming language of netlistsvg is JavaScript.
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