netlistsvg VS python-fpga-interchange

Maybe this: https://github.com/nturley/netlistsvg

Great article. Especially needed since Yosys is very difficult to use.

One tip, maybe. Yosys's Graphviz output is frankly incomprehensible shit, and Graphviz isn't very good at laying out these sorts of graphs. But it also can output the information to JSON with the write_json command which lets you use other better tools, e.g. https://github.com/nturley/netlistsvg

Soon: there are 15 different formats for passing netlists around.

I have very little hope that any netlist format that comes from Yosys. Not only has it changed a couple times in the last years, but the latest iteration is some JSON-based monstrosity that has to be by far the most inconvenient netlist format ever created (see https://github.com/nturley/netlistsvg/blob/master/test/digit... ) .

Or BLIF or EBLIF (already used by the verilog-to-routing flow). But no, let's invent yet another netlist format.

The fact that all of these existing formats are all named "xxx logic interchange format" should give you an idea what will happen to this new "interchange format".

From what I gather ( https://github.com/SymbiFlow/python-fpga-interchange/blob/ma... ) , the new format is basically the existing Yosys/nextpnr JSON format except dumped as a Cap'n Proto binary file.

I am absolutely not impressed.

I guess the meat here is on the universal device resources format, but this is not cool anyway.