wbuart32
A simple, basic, formally verified UART controller (by ZipCPU)
vgasim
A Video display simulator (by ZipCPU)
wbuart32 | vgasim | |
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4 | 11 | |
254 | 147 | |
- | - | |
4.6 | 1.2 | |
3 months ago | about 1 year ago | |
Verilog | Verilog | |
GNU General Public License v3.0 only | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
wbuart32
Posts with mentions or reviews of wbuart32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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CDC interview question clarification
Try this one.
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AXI Stream basics for beginners, Here's a video I made because a bunch of people suggested I do something AXI!
For example, some time after I built my own first serial port transmitter and receiver, someone tried using them in composition: A host (i.e. PC) would transmit a bunch of data, get received by the FPGA, processed by the receiver, and then the data would be sent back to the host via the transmitter. This is a hard test to get right, and my own design failed at the task. (It only returned every other byte!) What I learned from this is that the transmitter must take exactly (10*BAUD_CLOCKS) to transmit a byte. That also means that READY must be high on the last clock cycle of the byte to avoid falling behind. Let's just say that my own serial port wasn't (initially) up to the task. Among other things, the serial port receivers output "VALID" was only one cycle long, and didn't get latched anywhere if the transmitter wasn't ready for it. As I recall, we spent many days scratching our heads at the problem. Eventually, the person using my FPGA switched his host to sending 2-stop bits and things started working. Later, and only a long time later, did I ever find the off-by-one bug in the STOP bit state. My point? Serial port composition is an exacting test, and therefore a good one to work with. You ought to try it.
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How can I get Verilator to Prompt for User Input?
The core component to the single simulated to TCP port can be found here, in uartsim.cpp. You can find a companion software program that will forward the same TCP port to a hardware serial port here, under the name netuart.cpp.
vgasim
Posts with mentions or reviews of vgasim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
-
C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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Sobel algorithm in VHDL help
Most of the graphical images I've seen won't fit in block RAM on on an FPGA. (Think of an 800x600 pixel image, with 8bits per pixel, and it only gets worse from there.) The image needs to be stored elsewhere. That means, you need ports associated with feeding your image to your Sobel processor. This can happen one of two ways. You can either use a external Video frame buffer reader, or you can drive the memory bus yourself. You haven't said what type of memory bus your system has, so let me instead assume the external reader.
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Any good tips for writing IP that inputs/outputs AXI stream?
Definitely. To see how this might build up, consider this video sprite module. At each stage, counting from the end, the READY backs up.
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Simulate FPGA with other ICs
Ahm ... I've certainly added C components to my test bench to create and simulate graphical interfaces. Here's one for VGA, and another for HDMI. This isn't really a "nobody does this" task. It's much easier to debug a graphical component graphically than it is to debug it with a wave file. Indeed, I owe my success in one particular video decompression example to being able to stop the simulation in real time in order to find and trace a bug.
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More thorough resources for Verilator
Yes--I've done that with both VGA and HDMI. You can find the example here if you want to see how I did it.
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How does one verify audio- and video signal processing designs?
Check out this page describing these techniques, or even the repository containing my simulator.
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It's been three days and I couldn't find the problem. Any help is appreciated.
Why not try a Verilator based simulation like this one? You'd then be able to see the (broken) design on a window of your simulation host's screen, and capture a VCD file to see what's going on (or not)? You should be able to just place the VGA outputs into the VGASIM class to be able to see the image on your screen. Multiple video modes are supported, so select the one you need. (The demo works with all modes, but the memory mapped frame buffer's image is only built for 1280x1024, and hence the requirement in the demo).
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Is there a standard way of programming (Verilog) to use things that happen two or three clock cycles in the future?
For an example, you might wish to take a look at the histogram design I posted. Other valuable examples might include the slow filter, the slow linear phase filter, the downsampler, or even the FFT Window function. I've also got a sprite video design that I'd like to write about, but haven't had the chance to test yet. All of these designs need to deal with and work around these issues with internal block RAM.
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Need help with HDL testbench
I have a variety of C++ simulation sources that I use which can create either VGA or HDMI signals to input into a test bench--together with a couple example designs that demonstrate these test benches. They work nicely with Verilator.
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Getting DDR3 working on Arty-Z10
This demo shows how the AXI stream framed data can be turned to pixels and sent to a screen--should that be your wish.
What are some alternatives?
When comparing wbuart32 and vgasim you can also consider the following projects:
zipcpu - A small, light weight, RISC CPU soft core
biriscv - 32-bit Superscalar RISC-V CPU
wbicapetwo - Wishbone to ICAPE interface conversion
wb2axip - Bus bridges and other odds and ends
riscv - RISC-V CPU Core (RV32IM)
openarty - An Open Source configuration of the Arty platform
dpll - A collection of phase locked loop (PLL) related projects
FakePGA - Simulating Verilog designs on a microcontroller
fftdemo - A demonstration showing how several components can be compsed to build a simulated spectrogram