verilog_template
fusesoc_template
| verilog_template | fusesoc_template | |
|---|---|---|
| 1 | 1 | |
| 1 | 15 | |
| - | - | |
| 2.6 | 1.8 | |
| over 1 year ago | over 3 years ago | |
| Makefile | Python | |
| - | - |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilog_template
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(System)Verilog Linting in VSCode?
I have success with iverilog linting! Here is an example project with the settings configured: https://github.com/E4tHam/verilog_template
fusesoc_template
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Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
What are some alternatives?
Raylib-CPP-Starter-Template-for-VSCODE - Raylib C++ Starter Template for VSCODE
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
FPGA-blinky
RapidStream - This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools
edalize - An abstraction library for interfacing EDA tools
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
fpga-docker - Tools for running FPGA vendor toolchains with Docker
sv2v - SystemVerilog to Verilog conversion
golang-templates/seed - Go application GitHub repository template.