verilator VS naja-verilog

Compare verilator vs naja-verilog and see what are their differences.

verilator

Verilator open-source SystemVerilog simulator and lint system (by verilator)
Verilog system-verilog verilog-simulator Verilator Compilers CPP systemc Rtl
Source Code
verilator.org
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naja-verilog

A standalone structural (gate-level) verilog parser (by najaeda)
CPP eda netlist netlist-parser semiconductor Verilog electronic-design-automation Parser
Source Code
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verilator naja-verilog
11 2
2,098 21
5.1% -
9.8 7.6
about 9 hours ago 26 days ago
C++ C++
GNU Lesser General Public License v3.0 only Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

verilator

Posts with mentions or reviews of verilator. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-10-11.

naja-verilog

Posts with mentions or reviews of naja-verilog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-10-11.
  • Naja-Verilog: stand-alone structural (gate-level) parser
    2 projects | /r/FPGA | 11 Oct 2023
    Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
  • Show HN: Naja-Verilog – Structural Verilog Parser
    2 projects | news.ycombinator.com | 24 Mar 2023

What are some alternatives?

When comparing verilator and naja-verilog you can also consider the following projects:

wavedrom - :ocean: Digital timing diagram rendering engine

Degate - A modern and open-source cross-platform software for chips reverse engineering.

HLS-Tiny-Tutorials - This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

naja - Structural Netlist API (and more) for EDA post synthesis flow development

signalflip-js - verilator testbench w/ Javascript using N-API

spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.

verilator vs wavedrom naja-verilog vs Degate verilator vs HLS-Tiny-Tutorials naja-verilog vs hdlConvertor verilator vs riscv_vhdl naja-verilog vs Surelog verilator vs cva6 naja-verilog vs naja verilator vs signalflip-js naja-verilog vs spydrnet verilator vs Surelog verilator vs sphinxcontrib-hdl-diagrams