sv2v
verilog_template
sv2v | verilog_template | |
---|---|---|
3 | 1 | |
470 | 0 | |
- | - | |
7.6 | 2.6 | |
9 days ago | 9 months ago | |
Haskell | Makefile | |
BSD 3-clause "New" or "Revised" License | - |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
sv2v
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Verilog functions and wires
I see what you mean by some online examples adding begin...end in functions. They are not actually required, and many people choose to leave it out (sv2v, lowRISC, BSG). I don't believe there is a benefit to adding them, and it just creates more opportunities for bugs that compilers/linters cannot check.
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HDL desugaring
For verilog, I know SV2V exists: https://github.com/zachjs/sv2v
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Unrolling Verilog generate statements
Maybe this would help? https://github.com/zachjs/sv2v
verilog_template
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(System)Verilog Linting in VSCode?
I have success with iverilog linting! Here is an example project with the settings configured: https://github.com/E4tHam/verilog_template
What are some alternatives?
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Raylib-CPP-Starter-Template-for-VSCODE - Raylib C++ Starter Template for VSCODE
conversion - Universal converter between values of different types
fusesoc_template - Example of how to get started with olofk/fusesoc.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools
FPGA-blinky
fpga-docker - Tools for running FPGA vendor toolchains with Docker
edalize - An abstraction library for interfacing EDA tools
golang-templates/seed - Go application GitHub repository template.