sv2v
SystemVerilog to Verilog conversion (by zachjs)
conversion
Universal converter between values of different types (by nikita-volkov)
| sv2v | conversion | |
|---|---|---|
| 3 | - | |
| 470 | 7 | |
| - | - | |
| 7.6 | 0.0 | |
| 8 days ago | about 8 years ago | |
| Haskell | Haskell | |
| BSD 3-clause "New" or "Revised" License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
sv2v
Posts with mentions or reviews of sv2v.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Verilog functions and wires
I see what you mean by some online examples adding begin...end in functions. They are not actually required, and many people choose to leave it out (sv2v, lowRISC, BSG). I don't believe there is a benefit to adding them, and it just creates more opportunities for bugs that compilers/linters cannot check.
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HDL desugaring
For verilog, I know SV2V exists: https://github.com/zachjs/sv2v
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Unrolling Verilog generate statements
Maybe this would help? https://github.com/zachjs/sv2v
conversion
Posts with mentions or reviews of conversion.
We have used some of these posts to build our list of alternatives
and similar projects.
We haven't tracked posts mentioning conversion yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
When comparing sv2v and conversion you can also consider the following projects:
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
string-fromto - Conversions between common string types, as well as Base16/Base32/Base64
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.