spi-fpga
catapult-v3-smartnic-re
| spi-fpga | catapult-v3-smartnic-re | |
|---|---|---|
| 2 | 1 | |
| 157 | 94 | |
| - | - | |
| 0.0 | 2.2 | |
| about 3 years ago | 8 months ago | |
| VHDL | VHDL | |
| MIT License | - |
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spi-fpga
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The accelerometer on the CYC1000 FPGA board.
Last year I did experiments with the accelerometer on the CYC1000 FPGA board. The result is the Spirit Level example for my Git repository with SPI controllers. I also started using GHDL in GitHub Actions to automate my simulations. It is an easy-to-use CI for VHDL projects. https://github.com/jakubcabal/spi-fpga
- Does anyone have a Slave Quad SPI in VHDL?
catapult-v3-smartnic-re
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[FS] [CAN] 3x new Microsoft Azure Datacenter (Project Olympus) Motherboards and 1x new Microsoft Azure Datacenter FGPA Accelerator Card ( Project Catapult v3, Longs Peak edition)
The specs for the Project Catapult Longs Peak FGPA are a bit better known, even without testing (see here, together with pics):
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
w11 - PDP-11/70 CPU core and SoC
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
fpu - IEEE 754 floating point library in system-verilog and vhdl