sphinxcontrib-hdl-diagrams
fusesoc_template
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sphinxcontrib-hdl-diagrams | fusesoc_template | |
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2 | 1 | |
50 | 12 | |
- | - | |
5.7 | 1.8 | |
7 months ago | almost 3 years ago | |
Python | Python | |
Apache License 2.0 | - |
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sphinxcontrib-hdl-diagrams
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Is there any software I can use to transform state machines in VHDL into drawings?
Well, you can convert VHDL into Verilog using Icarus Verilog, and then you can draw a logic gate diagram (.svg file) to visualize your code using this: https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
- Systemverilog / verilog functional editor not like vivado
fusesoc_template
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Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
What are some alternatives?
verilator - Verilator open-source SystemVerilog simulator and lint system
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
sane_tikz - Reconquer the canvas: beautiful Tikz figures without clunky Tikz code
RapidStream - This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
edalize - An abstraction library for interfacing EDA tools
amaranth - A modern hardware definition language and toolchain based on Python
sphinx-tabs - Tabbed views for Sphinx
gdscript-docs-maker - Create documentation and class references from your Godot GDScript code
docs - Documentation site
sphinx-readme - Generate Beautiful reStructuredText README.rst for GitHub, PyPi, GitLab, BitBucket
tang-doc - Documentation for Lichee Tang