riscv-simple-sv VS riscv_verilator_model

Compare riscv-simple-sv vs riscv_verilator_model and see what are their differences.

riscv-simple-sv

A simple RISC V core for teaching (by tilk)
risc-v Riscv Verilog
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riscv_verilator_model

RISCV model for Verilator/FPGA targets (by aignacio)
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riscv-simple-sv riscv_verilator_model
2 2
145 40
- -
0.0 0.0
over 2 years ago over 4 years ago
SystemVerilog C
BSD 3-clause "New" or "Revised" License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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riscv-simple-sv

Posts with mentions or reviews of riscv-simple-sv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-10.
  • Simple CPU cores to study?
    3 projects | /r/Verilog | 10 Apr 2021
    I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
  • Need help in CPU design
    5 projects | /r/FPGA | 22 Mar 2021
    I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?

riscv_verilator_model

Posts with mentions or reviews of riscv_verilator_model. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-29.

What are some alternatives?

When comparing riscv-simple-sv and riscv_verilator_model you can also consider the following projects:

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

serv - SERV - The SErial RISC-V CPU

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

gdb-stub - gdb-proxy implementation for bonfire

picoMIPS - picoMIPS processor doing affine transformation

VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA

rhd - Tiny 16-bit RISC Core

FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA

riscv-simple-sv vs cv32e40p riscv_verilator_model vs serv riscv-simple-sv vs scr1 riscv_verilator_model vs neorv32 riscv-simple-sv vs gdb-stub riscv_verilator_model vs gdb-stub riscv-simple-sv vs picoMIPS riscv_verilator_model vs picoMIPS riscv-simple-sv vs neorv32 riscv-simple-sv vs VeriGPU riscv-simple-sv vs rhd riscv-simple-sv vs FPGA-Video-Processing