quasiSoC
No-MMU Linux capable RISC-V SoC designed to be useful. (by regymm)
Toast-RV32i
Pipelined RISC-V RV32I Core in Verilog (by georgeyhere)
| quasiSoC | Toast-RV32i | |
|---|---|---|
| 1 | 2 | |
| 91 | 34 | |
| - | - | |
| 6.4 | 0.0 | |
| 10 days ago | about 1 year ago | |
| C | C | |
| GNU General Public License v3.0 only | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
quasiSoC
Posts with mentions or reviews of quasiSoC.
We have used some of these posts to build our list of alternatives
and similar projects.
Toast-RV32i
Posts with mentions or reviews of Toast-RV32i.
We have used some of these posts to build our list of alternatives
and similar projects.
- Intermediate FPGA project suggestions for resume
-
RV32i RISCV processor for resume - Suggestions/feedback?
Github: https://github.com/georgeyhere/Toast-RV32i
What are some alternatives?
When comparing quasiSoC and Toast-RV32i you can also consider the following projects:
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
riscv - RISC-V CPU Core (RV32IM)
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
RVVM - The RISC-V Virtual Machine
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).
NyuziProcessor - GPGPU microprocessor architecture