cheshire
Arithmetic-Circuits
cheshire | Arithmetic-Circuits | |
---|---|---|
1 | 1 | |
107 | 3 | |
10.3% | - | |
7.6 | 3.8 | |
3 days ago | 8 months ago | |
SystemVerilog | SystemVerilog | |
GNU General Public License v3.0 or later | MIT License |
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cheshire
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Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
Arithmetic-Circuits
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Vivado doesn't generate flip flops
This is the entire code if you need to look: https://github.com/GabbedT/Arithmetic-Circuits/blob/main/Integer/Multipliers/pipelined_long_multiplier.sv
What are some alternatives?
hdmi - Send video/audio over HDMI on an FPGA
risc-v-single-cycle - A Single Cycle Risc-V 32 bit CPU
friscv - RISCV CPU implementation in SystemVerilog
pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
libsv - An open source, parameterized SystemVerilog digital hardware IP library
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
ApogeoRV - A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.