panologic-g2
rohd
| panologic-g2 | rohd | |
|---|---|---|
| 5 | 8 | |
| 130 | 350 | |
| - | 2.6% | |
| 0.0 | 8.0 | |
| almost 3 years ago | 15 days ago | |
| Verilog | Dart | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
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panologic-g2
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Chisel: A Modern Hardware Design Language
I've used SpinalHDL extensively for hobby projects, which is a close cousin of Chisel. The way it works there is by defining ClockDomain "areas" that contains logic for a particular clock/reset.
Signals can freely travel between different such areas, but unless you explicitly mark those signals as asynchronous, the Verilog code generator will fail with cross-domain clock violations. It's amazing.
Here's an example of an APB bridge with clock domain crossing: https://github.com/tomverbeure/panologic-g2/blob/ulpi/spinal....
The module takes the 2 domains as object parameters: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
Here's the code that lives in the APB clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
This is the destination clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
And this is the pulse synchronizer between them: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
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Reverse engineering unsocumented FPGA board?
I have reverse engineered many FPGA boards.
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Making my first game on FPGA
If you are okay with using a Spartan 6 device and ISE WebPACK, a Panologic G2 has 100k LUT6s, extra RAM and flash, Ethernet, USB, and two DVI/HDMI outputs, for under $50. Here's a github page, about developing for one.
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Looking for someone who has a good amount of FPGA's that are suitable for cracking bcrypt
If you send me a bitstream, I can try running it, but it will need to provide a way to communicate with the outside world, e.g. over the USB or Ethernet ports. There are hardware details here: https://github.com/tomverbeure/panologic-g2
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JTAG Programmer for Pano Logic G2?
I picked up a Pano Logic G2 for cheap and need to get a JTAG programmer for it. I'd like to use the Altera toolset. Is there an inexpensive JTAG programmer that I can use for this? I'm not at all familiar with JTAG and having a hard time figuring out what I'd miss out on by going with an off brand programmer.
rohd
- Intel/rohd: Hardware Development framework in the Dart programming language
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Chisel: A Modern Hardware Design Language
There's a similar project at Intel: https://github.com/intel/rohd
It uses Dart instead of Scala.
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Building a HDL (Kind of)
I've felt frustrated about SV and front end development for hardware and have been developing ROHD (https://github.com/intel/rohd) and it's been a worthwhile endeavor
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Discussion Thread
Dart is a general purpose language, there even is a hardware development framework by Intel which is made in Dart
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Choice of Python HDL library
Check out ROHD: https://github.com/intel/rohd
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[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​
You might be interested in checking out ROHD as well: https://github.com/intel/rohd
- Rapid Open Hardware Development (ROHD) Framework by Intel
What are some alternatives?
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