panologic-g2
pin-uart
| panologic-g2 | pin-uart | |
|---|---|---|
| 5 | 2 | |
| 130 | 24 | |
| - | - | |
| 0.0 | 2.9 | |
| almost 3 years ago | about 1 year ago | |
| Verilog | Tcl | |
| Apache License 2.0 | - |
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panologic-g2
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Chisel: A Modern Hardware Design Language
I've used SpinalHDL extensively for hobby projects, which is a close cousin of Chisel. The way it works there is by defining ClockDomain "areas" that contains logic for a particular clock/reset.
Signals can freely travel between different such areas, but unless you explicitly mark those signals as asynchronous, the Verilog code generator will fail with cross-domain clock violations. It's amazing.
Here's an example of an APB bridge with clock domain crossing: https://github.com/tomverbeure/panologic-g2/blob/ulpi/spinal....
The module takes the 2 domains as object parameters: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
Here's the code that lives in the APB clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
This is the destination clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
And this is the pulse synchronizer between them: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
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Reverse engineering unsocumented FPGA board?
I have reverse engineered many FPGA boards.
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Making my first game on FPGA
If you are okay with using a Spartan 6 device and ISE WebPACK, a Panologic G2 has 100k LUT6s, extra RAM and flash, Ethernet, USB, and two DVI/HDMI outputs, for under $50. Here's a github page, about developing for one.
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Looking for someone who has a good amount of FPGA's that are suitable for cracking bcrypt
If you send me a bitstream, I can try running it, but it will need to provide a way to communicate with the outside world, e.g. over the USB or Ethernet ports. There are hardware details here: https://github.com/tomverbeure/panologic-g2
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JTAG Programmer for Pano Logic G2?
I picked up a Pano Logic G2 for cheap and need to get a JTAG programmer for it. I'd like to use the Altera toolset. Is there an inexpensive JTAG programmer that I can use for this? I'm not at all familiar with JTAG and having a hard time figuring out what I'd miss out on by going with an off brand programmer.
pin-uart
- Pin UART FPGA board-level debugging and reverse-engineering tool
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Reverse engineering unsocumented FPGA board?
This concept can be handy, https://github.com/alexforencich/pin-uart
What are some alternatives?
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
clash-spaceinvaders - Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
panologic - PanoLogic Zero Client G1 reverse engineering info
make_for_vivado - experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
color3 - Information about eeColor Color3 HDMI FPGA board