panologic-g2 VS chipyard

I've used SpinalHDL extensively for hobby projects, which is a close cousin of Chisel. The way it works there is by defining ClockDomain "areas" that contains logic for a particular clock/reset.

Signals can freely travel between different such areas, but unless you explicitly mark those signals as asynchronous, the Verilog code generator will fail with cross-domain clock violations. It's amazing.

Here's an example of an APB bridge with clock domain crossing: https://github.com/tomverbeure/panologic-g2/blob/ulpi/spinal....

The module takes the 2 domains as object parameters: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...

Here's the code that lives in the APB clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...

This is the destination clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...

And this is the pulse synchronizer between them: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...

I have reverse engineered many FPGA boards.

If you are okay with using a Spartan 6 device and ISE WebPACK, a Panologic G2 has 100k LUT6s, extra RAM and flash, Ethernet, USB, and two DVI/HDMI outputs, for under $50. Here's a github page, about developing for one.

If you send me a bitstream, I can try running it, but it will need to provide a way to communicate with the outside world, e.g. over the USB or Ethernet ports. There are hardware details here: https://github.com/tomverbeure/panologic-g2

I picked up a Pano Logic G2 for cheap and need to get a JTAG programmer for it. I'd like to use the Altera toolset. Is there an inexpensive JTAG programmer that I can use for this? I'm not at all familiar with JTAG and having a hard time figuring out what I'd miss out on by going with an off brand programmer.

It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

[0]: https://github.com/ucb-bar/chipyard

[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

The repo in question is chipyard: https://github.com/ucb-bar/chipyard

Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

[1] https://github.com/ucb-bar/chipyard

[2] https://github.com/SpinalHDL/SpinalHDL

[3] https://github.com/B-Lang-org/bsc