rohd
verilog-ethernet
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rohd | verilog-ethernet | |
---|---|---|
8 | 32 | |
347 | 1,916 | |
3.5% | - | |
8.2 | 8.8 | |
11 days ago | about 2 months ago | |
Dart | Verilog | |
BSD 3-clause "New" or "Revised" License | MIT License |
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rohd
- Intel/rohd: Hardware Development framework in the Dart programming language
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Chisel: A Modern Hardware Design Language
There's a similar project at Intel: https://github.com/intel/rohd
It uses Dart instead of Scala.
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Building a HDL (Kind of)
I've felt frustrated about SV and front end development for hardware and have been developing ROHD (https://github.com/intel/rohd) and it's been a worthwhile endeavor
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Discussion Thread
Dart is a general purpose language, there even is a hardware development framework by Intel which is made in Dart
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Choice of Python HDL library
Check out ROHD: https://github.com/intel/rohd
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[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​
You might be interested in checking out ROHD as well: https://github.com/intel/rohd
- Rapid Open Hardware Development (ROHD) Framework by Intel
verilog-ethernet
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Quartus Tcl Build Script
Tcl, not sure, but I have done it with makefiles. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/C10LP/fpga.
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Using Si5324 as a clock generator on virtex-7 board
For that part I think you need to use the software from silicon labs (might be skyworks now) to generate the stuff you need to write to the registers. Then, you can use something like https://github.com/alexforencich/verilog-i2c/blob/master/rtl/i2c_init.v. See https://github.com/alexforencich/verilog-ethernet/tree/master/example/HTG9200/fpga_10g for an example that targets the Si5341 specifically.
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DE2-115 Ethernet Network Setup
For a personal project I'm trying to send data via Ethernet from my laptop into the FPGA, where it has some filtering and other processing done to it, then back into my laptop. I've been trying to get this repo to work, but there's a problem: my ancient macbook can't run Quartus, so I need to use campus PCs to build the project and program the board, but I don't have permissions to successfully run the makefiles that build the project.
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ROS 2 Humble in AMD KR260 with Yocto
No there's none. Not in this post at least, but it certain is being used. If you're interested in that, follow my progress at https://github.com/alexforencich/verilog-ethernet/issues/146 (or stay tuned/reach out to Acceleration Robotics for early previews and support) for a 10G NIC on the KR260.
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Choice of LFSR When implementing the ARP Cache in a UDP Stack
So, im trying to understand the UDP implementation in verilog-ethernet. In particular I am looking into the ARP Cache and have a query.
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Preference for Combinational or Sequential design?
I've been studying u/alexforencich's ethernet library since I'm working on a similar project. I've been noting his interesting design style. When I think about a solution for a problem, I immediately naturally thing about a sequential design whereas he has tons of combination logic in his designs.
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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Verilog Question- Setting a register concurrently twice in always block
I was studying Alex Forencich's FCS verilog and noticed the following always block:
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LiteX SGMII support
This repo support the VCU108 for a Verilog ethernet connection: https://github.com/alexforencich/verilog-ethernet
- Stream data into FPGA from PC
What are some alternatives?
cocotbext-axi - AXI interface modules for Cocotb
corundum - Open source FPGA-based NIC and platform for in-network compute
metroboy - A repository of gate-level simulators and tools for the original Game Boy.
litex - Build your hardware, easily!
hVHDL_floating_point - high level VHDL floating point library for synthesis in fpga
SpinalHDL - Scala based HDL
ResponsiveFramework - Easily make Flutter apps responsive. Automatically adapt UI to different screen sizes. Responsiveness made simple. Demo: https://gallery.codelessly.com/flutterwebsites/minimal/
embox - Modular and configurable OS for embedded applications
aqueduct - Dart HTTP server framework for building REST APIs. Includes PostgreSQL ORM and OAuth2 provider.
pygears - HW Design: A Functional Approach
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.