panologic-g2
chisel
panologic-g2 | chisel | |
---|---|---|
5 | 25 | |
130 | 3,717 | |
- | 1.1% | |
0.0 | 9.7 | |
almost 3 years ago | 8 days ago | |
Verilog | Scala | |
Apache License 2.0 | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
panologic-g2
-
Chisel: A Modern Hardware Design Language
I've used SpinalHDL extensively for hobby projects, which is a close cousin of Chisel. The way it works there is by defining ClockDomain "areas" that contains logic for a particular clock/reset.
Signals can freely travel between different such areas, but unless you explicitly mark those signals as asynchronous, the Verilog code generator will fail with cross-domain clock violations. It's amazing.
Here's an example of an APB bridge with clock domain crossing: https://github.com/tomverbeure/panologic-g2/blob/ulpi/spinal....
The module takes the 2 domains as object parameters: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
Here's the code that lives in the APB clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
This is the destination clock domain: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
And this is the pulse synchronizer between them: https://github.com/tomverbeure/panologic-g2/blob/9225b86011a...
-
Reverse engineering unsocumented FPGA board?
I have reverse engineered many FPGA boards.
-
Making my first game on FPGA
If you are okay with using a Spartan 6 device and ISE WebPACK, a Panologic G2 has 100k LUT6s, extra RAM and flash, Ethernet, USB, and two DVI/HDMI outputs, for under $50. Here's a github page, about developing for one.
-
Looking for someone who has a good amount of FPGA's that are suitable for cracking bcrypt
If you send me a bitstream, I can try running it, but it will need to provide a way to communicate with the outside world, e.g. over the USB or Ethernet ports. There are hardware details here: https://github.com/tomverbeure/panologic-g2
-
JTAG Programmer for Pano Logic G2?
I picked up a Pano Logic G2 for cheap and need to get a JTAG programmer for it. I'd like to use the Altera toolset. Is there an inexpensive JTAG programmer that I can use for this? I'm not at all familiar with JTAG and having a hard time figuring out what I'd miss out on by going with an off brand programmer.
chisel
-
Calyx: Intermediate Language for Hardware Accelerators
My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.
I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.
That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."
A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.
There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].
1: https://www.chisel-lang.org
2: https://github.com/sarchlab/akita
- Chisel: A Modern Hardware Design Language
-
I may be creating an abomination
Inspired by Scala. Which can do a whole lot more, and worse. The currently biggest competitor to decades old hardware description languages is a Scala DSL.
-
An addressable little explored language gap: HDL - Hardware Description Languages, any language used for electronic circuit design, description, and specs
Already mentioned Chisel: https://www.chisel-lang.org/
-
Trying to learn and work with FPGAs
I'm also a hobbyist. There are a number of alternative HDLs out there, and as hobbyists we can deviate more from the mainstream of (System)Verilog and VHDL if we desire, though you'll still need to be able to read them. In the past I've done Verilog, but lately I've been using SpinalHDL and have been really enjoying it. Its close relative Chisel also makes appearances in the RISC-V space.
- Alternate HDL language and Physical Design/EDA tools?
-
Learning VDHL after knowing Verilog
What are your thoughts on other HDLs like Chisel or BlueSpec when it comes to better type checking?
-
Learning Verilog and FPGA
I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better.
I chose Chisel (https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.
I'd highly advise looking into it although also knowing Verilog helps a lot.
-
If you keep clicking "Give 15 seconds" on Lichess, eventually it overflows to a negative number and you win
But some go further and ask "what if when we add a soldering station on top of it?"
-
What universities have good PhD programmes in digital design?
In recent years Chisel HDL, RISC V, and SiFive came out of their architecture group, to name a few.
What are some alternatives?
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
SpinalHDL - Scala based HDL
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
myhdl - The MyHDL development repository
pin-uart - FPGA board-level debugging and reverse-engineering tool
amaranth - A modern hardware definition language and toolchain based on Python
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
bsc - Bluespec Compiler (BSC)
circt - Circuit IR Compilers and Tools
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
XiangShan - Open-source high-performance RISC-V processor