Learning Verilog and FPGA

• vhdl-tutorial

  1 65 4.0 VHDL
  

Greg Stitt shares amazing training materials freely (he uses them for his undergraduate and graduate courses). His synthesizable HDL methods are really empowering for beginner developers

https://github.com/ARC-Lab-UF/vhdl-tutorial

http://www.gstitt.ece.ufl.edu/

• f4pga-arch-defs

  19 247 7.7 Jupyter Notebook

  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

  

QuickLogic [1] seems to support and target the open tool environment for their devices -especially the F4PGA [2] toolkit (known earlier as symbiflow). Others have mentioned Lattice FPGAs. But the impression I got from Lattice is that they like the development of open tools, but don't want to invest too much in it. QuickLogic on the other hand, contribute code and design directly to F4PGA project and allied ones like Migen.

[1]: https://www.quicklogic.com/software/qorc-mcu-efpga-fpga-open...

[2]: https://f4pga.org/

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• icestorm

  7 945 0.0 Python

  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

  

As others have already mentioned the Lattice ice40 family is supported by OSS chains through project icestorm [0].

There were some nice boards floating around though you may have to watch out for supply chain issues still plaguing this market. Examples:

- icoboard: has the 8k LUTs chip, comes with soldered PMODs[1], if you get it watch out as you either need a RaspberryPI with GPIOs soldered to program it, or you purchase their USB FTDI interface in addition. See: http://icoboard.org/

- iCEBreaker, comes with the 5k LUTs chip, has the USB-FTDI interface built-in, but you need to solder the PMODs yourself. See: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga#prod...

[0] https://github.com/YosysHQ/icestorm

• prince

  1 7 3.5 Verilog

  The Prince lightweight block cipher in Verilog.

I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS on a statement has been updated.

IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.

https://github.com/secworks/prince/blob/master/src/rtl/princ...

The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.

• apio

  3 753 9.7 Verilog

  :seedling: Open source ecosystem for open FPGA boards

  

I've had good experiences using Upduino 3.0 and 3.1 [0] with the IceStorm tools via apio [1]. I wrote a blog post [2] with some info on getting things set up via Linux. All you need is the Upduino board, which interfaces to your host system via USB (so no special programmer is needed).

[0] https://tinyvision.ai/products/upduino-v3-1

[1] https://github.com/FPGAwars/apio

[2] https://daveho.github.io/2021/02/07/upduino3-getting-started...

• prjtrellis

  5 381 8.5 Python

  Documenting the Lattice ECP5 bit-stream format.

  

Yosys, the underlying compiler of ice studio, also targets the much bigger ECP5 FPGA, also by Lattice, which is called Project Trellis: https://github.com/YosysHQ/prjtrellis

Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use.

In general the hardware toolchains feel very ancient compared to software toolchains.

• chisel

  25 3,708 9.7 Scala

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

I started playing with FPGAs and HDLs a couple years ago with no hardware design background (I'm mostly a software architect/engineer) and in the end found that a "higher-level" HDL suited me better.

I chose Chisel (https://www.chisel-lang.org/) an HDL based on Scala (technically a Scala DSL) which can provide many facilities to hardware generation.

I'd highly advise looking into it although also knowing Verilog helps a lot.

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• 6502-exp

  1 0 10.0 Assembly

  6502 Computer FPGA Peripherals

Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chisel project. Therefore it is already supported by practically all vendors and simulators.

I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...

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