openlane VS ALIGN-public

Compare openlane vs ALIGN-public and see what are their differences.

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. (by efabless)
InfluxDB - Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com
featured
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com
featured
openlane ALIGN-public
12 3
1,179 232
2.6% -
8.4 8.1
7 days ago 10 days ago
Python C++
Apache License 2.0 BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

openlane

Posts with mentions or reviews of openlane. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-15.
  • [D][P] Represent Analog Circuits as Graphs
    3 projects | /r/MachineLearning | 15 Apr 2023
    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
  • how small team survive from cadence cost
    1 project | /r/chipdesign | 15 Jan 2023
    There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane
  • VLSI Tools
    6 projects | /r/chipdesign | 14 Dec 2022
    OpenLane
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
  • Kickstarting IC design
    2 projects | /r/chipdesign | 3 Dec 2021
    And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
  • How are modern processors and their architecture designed?
    4 projects | /r/ECE | 28 Sep 2021
    For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
  • Project Ideas for Uni
    2 projects | /r/FPGA | 23 Aug 2021
    Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
  • ASIC design post layout for padding.
    1 project | /r/chipdesign | 15 Aug 2021
    I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane
  • Resources for a physical design engineer
    1 project | /r/chipdesign | 20 Jul 2021
    Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
  • Intro into chip design
    1 project | /r/chipdesign | 7 May 2021
    https://github.com/efabless/openlane The README is very helpful

ALIGN-public

Posts with mentions or reviews of ALIGN-public. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-04-15.
  • [D][P] Represent Analog Circuits as Graphs
    3 projects | /r/MachineLearning | 15 Apr 2023
    I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
  • What's the best public FinFET PDK PDK?
    3 projects | /r/chipdesign | 6 Nov 2022
    Hi folks, I am looking for a FinFET PDK that's accessible publicly. The best one I can find is from ALIGN. There's a paper on FreePDK15 but it seems I can't access the website they mentioned. There's also ASAP7, but it seems they are lacking publicly available DRC and LVS. I requested more ASAP7 resources using my student email but haven't heard from them yet. Any tips on the available resource or how should I approach these ones I mentioned?
  • Why automating analog layouts so difficult?
    1 project | /r/chipdesign | 21 Oct 2022

What are some alternatives?

When comparing openlane and ALIGN-public you can also consider the following projects:

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

ASAP7_for_KLayout - KLayout technology files for ASAP7 FinFET educational process

picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU

asap7

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

rocket-chip - Rocket Chip Generator

NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上

riscv - RISC-V CPU Core (RV32IM)

opentitan - OpenTitan: Open source silicon root of trust

sv2v - SystemVerilog to Verilog conversion

zerosoc - Demo SoC for SiliconCompiler.

Verilog.jl - Verilog for Julia