openlane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization. (by efabless)
sv2v
SystemVerilog to Verilog conversion (by zachjs)
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| openlane | sv2v | |
|---|---|---|
| 12 | 3 | |
| 1,174 | 464 | |
| 4.8% | - | |
| 8.6 | 7.6 | |
| 8 days ago | 9 days ago | |
| Python | Haskell | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
openlane
Posts with mentions or reviews of openlane.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-04-15.
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[D][P] Represent Analog Circuits as Graphs
I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
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how small team survive from cadence cost
There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane
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VLSI Tools
OpenLane
- Compiling Code into Silicon
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Kickstarting IC design
And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
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How are modern processors and their architecture designed?
For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
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Project Ideas for Uni
Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
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ASIC design post layout for padding.
I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane
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Resources for a physical design engineer
Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
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Intro into chip design
https://github.com/efabless/openlane The README is very helpful
sv2v
Posts with mentions or reviews of sv2v.
We have used some of these posts to build our list of alternatives
and similar projects.
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Verilog functions and wires
I see what you mean by some online examples adding begin...end in functions. They are not actually required, and many people choose to leave it out (sv2v, lowRISC, BSG). I don't believe there is a benefit to adding them, and it just creates more opportunities for bugs that compilers/linters cannot check.
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HDL desugaring
For verilog, I know SV2V exists: https://github.com/zachjs/sv2v
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Unrolling Verilog generate statements
Maybe this would help? https://github.com/zachjs/sv2v
What are some alternatives?
When comparing openlane and sv2v you can also consider the following projects:
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
conversion - Universal converter between values of different types
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
rocket-chip - Rocket Chip Generator
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
riscv - RISC-V CPU Core (RV32IM)
opentitan - OpenTitan: Open source silicon root of trust
zerosoc - Demo SoC for SiliconCompiler.
Verilog.jl - Verilog for Julia
Slime-Simulation