o1heap
Vitis-Tutorials
| o1heap | Vitis-Tutorials | |
|---|---|---|
| 4 | 4 | |
| 215 | 1,063 | |
| - | 2.6% | |
| 1.7 | 9.3 | |
| about 1 year ago | 20 days ago | |
| C++ | C | |
| MIT License | MIT License |
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o1heap
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I have 16 gigabytes of RAM and I am going to use 16 gigabytes of RAM.
https://github.com/pavel-kirienko/o1heap lol u think you’re kidding
- O1heap: Constant-complexity deterministic memory allocator for embedded systems
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using heap in baremetal embedded
Another option is using an allocator that provides some guarantees that work for your use case, eg https://github.com/pavel-kirienko/o1heap
Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
What are some alternatives?
memory - STL compatible C++ memory allocator library using a new RawAllocator concept that is similar to an Allocator but easier to use and write.
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
fprime - F´ - A flight software and embedded systems framework
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
real-time-cpp - Source code for the book Real-Time C++, by Christopher Kormanyos
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
luos_engine - Open-source and real-time orchestrator for cyber-physical-systems, to easily design, test and deploy embedded applications and digital twins.
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
snmalloc - Message passing based allocator
Vitis-HLS-Introductory-Examples
Mesh - A memory allocator that automatically reduces the memory footprint of C/C++ applications.
Vitis_Accel_Examples - Vitis_Accel_Examples