Xilinx HLS AXI4-Lite registers don't update right away

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  4 1,068 9.3 C

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Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {

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