Vitis-Tutorials
finn-examples
Vitis-Tutorials | finn-examples | |
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4 | 1 | |
1,068 | 160 | |
3.1% | 3.8% | |
9.3 | 0.0 | |
25 days ago | 5 days ago | |
C | Jupyter Notebook | |
MIT License | BSD 3-clause "New" or "Revised" License |
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Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
finn-examples
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Simplifying AI to FPGA deployment, looking for opportunities
FINN can implement arbitrary and mixed precision DNNs, not just BNNs. There is an examples git repo: https://github.com/Xilinx/finn-examples
What are some alternatives?
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
o1heap - Constant-complexity deterministic memory allocator (heap) for hard real-time high-integrity embedded systems. There is very little activity because the project is finished and does not require further changes.
larq - An Open-Source Library for Training Binarized Neural Networks
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
rfsoc_studio - The Strathclyde RFSoC Studio Installer for PYNQ.
Vitis-HLS-Introductory-Examples
Vitis_Accel_Examples - Vitis_Accel_Examples
PYNQ - Python Productivity for ZYNQ