Vitis-Tutorials
| Vitis-Tutorials | Vitis-HLS-Introductory-Examples | |
|---|---|---|
| 4 | 4 | |
| 1,068 | 522 | |
| 3.1% | 4.9% | |
| 9.3 | 6.3 | |
| 25 days ago | 13 days ago | |
| C | C++ | |
| MIT License | GNU General Public License v3.0 or later |
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Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
Vitis-HLS-Introductory-Examples
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Roadblocks to HLS development
Synthesis errors on Windows 10 platform - I had installed 2023.2 versions of Vivado and standalone Vitis HLS tools. I had trouble synthesizing and simulating the HLS examples in Vitis HLS. I think this had something to do with the compiler not able to deal with OpenCV libraries. I had cloned the opencv libraries but struggled to understand the instructions given below (which I guess is meant for a linux machine). Also during its launch, the standalone tool keeps stating that it will get deprecated in the future.
- Vivado editor alternatives
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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What is wrong with the following code in vivado hls?
HLS Tiny Tutorials
What are some alternatives?
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
o1heap - Constant-complexity deterministic memory allocator (heap) for hard real-time high-integrity embedded systems. There is very little activity because the project is finished and does not require further changes.
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
Vitis_Accel_Examples - Vitis_Accel_Examples
XRT - Run Time for AIE and FPGA based platforms
EmbeddedProto - Embedded Proto is a C++ Protocol Buffers implementation specifically suitable for microcontrollers. It is small, reliable and easy to use.