Vitis-Tutorials
esp
| Vitis-Tutorials | esp | |
|---|---|---|
| 4 | 1 | |
| 1,068 | 297 | |
| 3.1% | 2.0% | |
| 9.3 | 7.5 | |
| 25 days ago | 19 days ago | |
| C | C | |
| MIT License | GNU General Public License v3.0 or later |
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Vitis-Tutorials
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How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
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Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
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Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
esp
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
What are some alternatives?
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
ara - The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
Vitis-HLS-Introductory-Examples
o1heap - Constant-complexity deterministic memory allocator (heap) for hard real-time high-integrity embedded systems. There is very little activity because the project is finished and does not require further changes.
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
litex - Build your hardware, easily!