Vitis-Tutorials
o1heap
Vitis-Tutorials | o1heap | |
---|---|---|
4 | 4 | |
1,068 | 215 | |
3.1% | - | |
9.3 | 1.7 | |
25 days ago | about 1 year ago | |
C | C++ | |
MIT License | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Vitis-Tutorials
-
How to use maximum HBM bandwidth?
Currently, I am only reading/writing 64 bits with each access (code below). I found a sample code in the Xilinx repository (link) that utilizes all 512 bits of an AXI port, but I am struggling with how to use parallel AXI ports (32 ports). I would greatly appreciate any hints or guidance on this.
-
Xilinx HLS AXI4-Lite registers don't update right away
Here is the top level function. It is a modified version of the convolution HLS provided in one of Xilinx's Vitis tutorials. I've run into a similar problem for other HLS IP where the AXI4-Lite registers don't update right away. ``` void Filter2DKernel( const float coeffs[MAX_COEFFS], float factor, short bias, unsigned short width, unsigned short height, unsigned short stride, hls::stream &input_stream, hls::stream &output_stream) {
-
Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
-
Xilinx expensive accelerate card
Here are some resources: 1. Vitis AI on Custom Platform 2. Vitis Platform Creation
o1heap
-
I have 16 gigabytes of RAM and I am going to use 16 gigabytes of RAM.
https://github.com/pavel-kirienko/o1heap lol u think you’re kidding
- O1heap: Constant-complexity deterministic memory allocator for embedded systems
-
using heap in baremetal embedded
Another option is using an allocator that provides some guarantees that work for your use case, eg https://github.com/pavel-kirienko/o1heap
What are some alternatives?
finn-examples - Dataflow QNN inference accelerator examples on FPGAs
memory - STL compatible C++ memory allocator library using a new RawAllocator concept that is similar to an Allocator but easier to use and write.
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
fprime - F´ - A flight software and embedded systems framework
lfbb - A Lock Free Bipartite Buffer Library written in standard C11
real-time-cpp - Source code for the book Real-Time C++, by Christopher Kormanyos
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
luos_engine - Open-source and real-time orchestrator for cyber-physical-systems, to easily design, test and deploy embedded applications and digital twins.
Vitis-HLS-Introductory-Examples
snmalloc - Message passing based allocator
Vitis_Accel_Examples - Vitis_Accel_Examples
Mesh - A memory allocator that automatically reduces the memory footprint of C/C++ applications.