neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains. (by stnolting)
ORCA-risc-v
RISC-V by VectorBlox (by kammoh)
Our great sponsors
| neorv32-setups | ORCA-risc-v | |
|---|---|---|
| 5 | 1 | |
| 52 | 13 | |
| - | - | |
| 8.6 | 10.0 | |
| 6 days ago | over 8 years ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32-setups
Posts with mentions or reviews of neorv32-setups.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-20.
-
How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
-
A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
-
Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
ORCA-risc-v
Posts with mentions or reviews of ORCA-risc-v.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-28.
-
Open-source RISC-V CPU projects for contribution
Orca: https://github.com/kammoh/ORCA-risc-v
What are some alternatives?
When comparing neorv32-setups and ORCA-risc-v you can also consider the following projects:
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
openc910 - OpenXuantie - OpenC910 Core
litex - Build your hardware, easily!
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
vroom - VRoom! RISC-V CPU
fpu - IEEE 754 floating point library in system-verilog and vhdl
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
neorv32-setups vs picorv32
ORCA-risc-v vs openc910
neorv32-setups vs litex
ORCA-risc-v vs riscv-boom
neorv32-setups vs neorv32
ORCA-risc-v vs vroom
neorv32-setups vs fpu
ORCA-risc-v vs picorv32
neorv32-setups vs neoTRNG
ORCA-risc-v vs vivado-risc-v
neorv32-setups vs vivado-risc-v
neorv32-setups vs riscv-boom