neo430
betrusted-wiki
| neo430 | betrusted-wiki | |
|---|---|---|
| 3 | 3 | |
| 178 | 171 | |
| - | 2.3% | |
| 2.8 | 0.0 | |
| over 2 years ago | about 3 years ago | |
| VHDL | ||
| BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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neo430
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
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Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
betrusted-wiki
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Hardware Random Bit Generator
Bunnie Hwang's "Betrusted" project uses a pair of circuits as an entropy source, with a few blog posts describing the how and why of the design.
One source is a ring oscillator, internal to the Betrusted FPGA. The other is an avalanche noise source similar to OP, external to the FPGA.
The two streams are XOR'd and then run through a cryptographic hash.
https://github.com/betrusted-io/betrusted-wiki/wiki/TRNG-cha...
https://github.com/betrusted-io/betrusted-wiki/wiki/TRNG-Dat...
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Is there any reliable guide for creating an operating system in Rust?
In addition to phil-opp and redox, there's the Betrusted project's Xous kernel, which runs on a RISC-V core that runs on an FPGA. There's even an Xous Book.
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The NEO430 Processor
You might be interested in https://github.com/betrusted-io/betrusted-wiki/wiki/TRNG-cha...
What are some alternatives?
serv - SERV - The SErial RISC-V CPU
rust-os-comparison - A comparison of operating systems written in Rust
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
xous-core - The Xous microkernel
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
Beautiful docs - Pointers to useful, well-written, and otherwise beautiful documentation.
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
the-art-of-command-line - Master the command line, in one page
SoC - Github Repo for Embedded FPGA course by Vincent Claes
lemonade-stand - A handy guide to financial support for open source