ndk-app-minimal
spi-fpga
ndk-app-minimal | spi-fpga | |
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4 | 2 | |
23 | 157 | |
- | - | |
8.2 | 0.0 | |
17 days ago | about 3 years ago | |
VHDL | VHDL | |
BSD 3-clause "New" or "Revised" License | MIT License |
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ndk-app-minimal
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A simple high-throughput open-source packet generator
as the title says, I'm looking to build a simple packet generator (a PCAP (re)player might be a better term), mainly for load-testing network devices. The goal is to be able to fully congest a 400G Ethernet line. To achieve such a high throughput rate, I plan to use the NDK platform to build my application.
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Xilinx alternatives??
We have few Intel Agilex I-Series FPGA boards in our lab. It can do 400G Ethernet 8x56Gb or 4x112Gb (F-Tile), PCIe Gen5 x16 (R-Tile) and CXL IP is for a fee, I think. You can find an example of using F/R-Tile in our open-source NDK: https://github.com/CESNET/ndk-app-minimal
- The Network Development Kit for FPGA cards in version 0.3.1 released
- The Network Development Kit for FPGA cards released as open-source
spi-fpga
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The accelerometer on the CYC1000 FPGA board.
Last year I did experiments with the accelerometer on the CYC1000 FPGA board. The result is the Spirit Level example for my Git repository with SPI controllers. I also started using GHDL in GitHub Actions to automate my simulations. It is an easy-to-use CI for VHDL projects. https://github.com/jakubcabal/spi-fpga
- Does anyone have a Slave Quad SPI in VHDL?
What are some alternatives?
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
w11 - PDP-11/70 CPU core and SoC
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
fpu - IEEE 754 floating point library in system-verilog and vhdl
sdram-fpga - A FPGA core for a simple SDRAM controller.