gmid
OpenTimer
| gmid | OpenTimer | |
|---|---|---|
| 1 | 1 | |
| 37 | 516 | |
| - | 2.3% | |
| 6.1 | 0.0 | |
| 2 months ago | 12 months ago | |
| Python | Verilog | |
| MIT License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
gmid
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Tool for making transistor plots such as the one for the gm/id methodology written in Python
I wrote a simple tool that automatically generates a lookup table for a given MOS model and then make all sorts of plots (and much more) with as little effort as possible. I thought I'd share it. You can find it here. If you find it useful and have a specific use case, I'll be happy to consider it.
OpenTimer
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Topology sort open source
One application that uses topological sorting is claimed timing analysis. https://github.com/OpenTimer/OpenTimer
What are some alternatives?
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ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
hdl - HDL libraries and projects
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serv - SERV - The SErial RISC-V CPU
dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.
spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OpenLANE-Sky130-Physical-Design-Workshop - Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130