gssi
edalize
| gssi | edalize | |
|---|---|---|
| 1 | 4 | |
| 3 | 593 | |
| - | - | |
| 10.0 | 7.2 | |
| over 5 years ago | 5 days ago | |
| TeX | Python | |
| GNU General Public License v3.0 or later | BSD 2-clause "Simplified" License |
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gssi
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Compiling Code into Silicon
Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way.
[0]: https://www.myhdl.org/
[1]: https://github.com/lou1306/gssi/tree/master/2pc
edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
Verilog.jl - Verilog for Julia
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
apio - :seedling: Open source ecosystem for open FPGA boards
zerosoc - Demo SoC for SiliconCompiler.
icestudio - :snowflake: Visual editor for open FPGA boards
opentitan - OpenTitan: Open source silicon root of trust
rggen - Code generation tool for control and status registers