gssi
Verilog.jl
| gssi | Verilog.jl | |
|---|---|---|
| 1 | 2 | |
| 3 | 46 | |
| - | - | |
| 10.0 | 0.0 | |
| over 5 years ago | about 7 years ago | |
| TeX | Julia | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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gssi
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Compiling Code into Silicon
Personally I have fond memories of MyHDL [0], which may be seen as another "code-to-silicon" converter (or at least as the first step of a code-to-silicon workflow). I used it only briefly, and on a school project that had surprisingly little to do with actual hardware design [1], but it really felt "Pythonic" in the best possible way.
[0]: https://www.myhdl.org/
[1]: https://github.com/lou1306/gssi/tree/master/2pc
Verilog.jl
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Compiling Code into Silicon
It doesn't have to be. I once made a julia->verilog transpiler that even recompiled your julia functions with verilator, so you could verify that the code was correct.
https://github.com/interplanetary-robot/Verilog.jl
Of course, gaining traction on something like this is tricky.
I actually think Erlang/BEAM would be a great choice for making EDA tools, because it has concurrent execution model that you could probably very easily make play nice in rudimentary simulations of circuits that have triggers (`always @` sort of stuff.
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Julia Receives DARPA Award to Accelerate Electronics Simulation by 1,000x
A long long long time ago, I wrote this (currently very unmaintained) julia project, don't know if this is useful to you, but it's pretty clear that there is a LOT of potential for julia in this domain: https://github.com/interplanetary-robot/Verilog.jl
What are some alternatives?
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
Octavian.jl - Multi-threaded BLAS-like library that provides pure Julia matrix multiplication
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
edalize - An abstraction library for interfacing EDA tools
svls - SystemVerilog language server
zerosoc - Demo SoC for SiliconCompiler.
Modia.jl - Modeling and simulation of multidomain engineering systems
opentitan - OpenTitan: Open source silicon root of trust
Automa.jl - A julia code generator for regular expressions