friscv VS jtag_uart_example

Compare friscv vs jtag_uart_example and see what are their differences.

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friscv jtag_uart_example
1 1
15 16
- -
7.7 0.0
7 days ago almost 3 years ago
Coq Verilog
MIT License The Unlicense
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

friscv

Posts with mentions or reviews of friscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-22.

jtag_uart_example

Posts with mentions or reviews of jtag_uart_example. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-22.

What are some alternatives?

When comparing friscv and jtag_uart_example you can also consider the following projects:

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

Cores-VeeR-EH1 - VeeR EH1 core

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

fpga_riscv_cpu - fpga verilog risc-v rv32i cpu

riscv - RISC-V CPU Core (RV32IM)