jtag_uart_example

Mini CPU design with JTAG UART support (by tomverbeure)

Jtag_uart_example Alternatives

Similar projects and alternatives to jtag_uart_example

  • GitHub repo friscv

    RISCV CPU implementation in SystemVerilog

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Posts

Posts where jtag_uart_example has been mentioned. We have used some of these posts to build our list of alternatives and similar projects - the last one was on 2021-06-22.
  • Need help learning how to use risc-v toolchain
    reddit.com/r/FPGA | 2021-06-22
    Here is one such example.

Stats

Basic jtag_uart_example repo stats
1
8
5.0
about 2 months ago

tomverbeure/jtag_uart_example is an open source project licensed under The Unlicense which is not an OSI approved license.