Similar projects and alternatives to jtag_uart_example
RISCV CPU implementation in SystemVerilog
NOTE: The number of mentions on this list indicates mentions on common posts. Hence, a higher number means a better jtag_uart_example alternative or higher similarity.
Posts where jtag_uart_example has been mentioned. We have used some of these posts to build our list of alternatives and similar projects - the last one was on 2021-06-22.
Need help learning how to use risc-v toolchain
reddit.com/r/FPGA | 2021-06-22
Here is one such example.
Basic jtag_uart_example repo stats
about 2 months ago
tomverbeure/jtag_uart_example is an open source project licensed under The Unlicense which is not an OSI approved license.